The present invention relates to Integrated Circuits (ICs) and semiconductor devices and their methods of manufacture wherein the semiconductor devices provide semiconductor memories, such as ROMs, EPROMs or EEPROMs, and have bit line block protection circuitry and/or word line block protection circuitry to inhibit or prevent the unauthorized reading of data stored in the semiconductor device by a party interested in, for example, reverse engineering the IC or system.
Data and software can be very valuable and those involved in the collection of data and those involved in preparation of software will often go to great lengths to try to protect the data and/or software from unauthorized parties. In modern electronic devices, data and software are often stored in memory, and more particularly in ICs or systems which include memory in the form of an array of memory cells. FIG. 1 depicts a schematic of a conventional memory array formed of an array of memory cells 22. The cells 22 are addressed by signals appearing on (i) row or word lines 21 in combination with signals appearing on column or bit lines 20. The array shown in FIG. 1 represents only a very small portion of memory since a modern memory IC have millions of such cells 22. The individual cells 22 can be in the form of ROM, RAM, EPROM, EEPROM, etc., cells, as is known in the art. Each individual memory cell 22 could be as simple as a programmable junction or it can represent a memory circuit. The details of how the individual cells 22 are implemented are not important in terms of the present invention.
The design and development of software and/or data associated with semiconductor Integrated Circuits (ICs) tend to be rather expensive and, in fact, many hours of software engineering talent is required to develop such software and/or data. The software and/or data are stored in memories associated with the ICs, the memories either comprising on-board memories (where the memory is integrated with other elements such as data processors, digital signal processors, CPU""s and the like) or comprising separate, discrete memory devices. In either case the memory is typically formed by an array of memory cells such as that depicted by FIG. 1.The software and/or data may be stored permanently in the memory or the software and/or data may be erasable and/or may be dynamic. The ICs themselves may be Application Specific ICs (ASICs) or regular off-the-shelf components or devices.
If the data and/or software are valuable, then reverse engineers are apt to try to get at the software and/or data. Since software may be considered as a type of data, the term data as used herein is intended to refer to any kind of data whatsoever, including application software and/or firmware. If the software is stored more or less permanently on an IC it is not infrequently referred to as firmware. As such, the term data as used herein also includes firmware.
Some in the art avoid both the expense involved in the design and development of data and the significant time involved in bringing a new integrated circuit design, which might include data stored therein, to the marketplace, by resorting to reverse engineering practices that take apart, probe, and otherwise examine existing ICs. Their purpose is to try to determine the physical structures and methods used to make the integrated circuit for purposes of subsequent copying. They also try to read the data stored in such ICs. This reverse engineering, which often relies on obtaining planar optical images of a circuit or on reading out data stored on an IC via its external or internal connections, in essence tries to bypass the typical product development cycles and expenses involved in producing integrated circuits and/or the data used therewith.
Since the reverse engineer is trying to go for axe2x80x9cfree ridexe2x80x9d on the efforts of others, various approaches have been developed to try to thwart the reverse engineer in the field of semiconductor devices, including devices which have memory for storing data. If the semiconductor device is a memory device or an IC bike containing memory, the data stored in such memory is usually read out on bit lines in response to an address placed on an address line. These bit and address lines may be more or less easily accessible from external physical connections on an IC or the bit and address lines may be buried within an IC so that they are not readily accessible by making external connections to the IC. Different techniques have been used to try to thwart the reverse engineer in the prior art. For example, metal layers have been disposed over memory, which metal is tied to either a high or low potential, but isolated from the memory itself, to try to protect the memory from being read using Scanning Electron Microscopy (SEM) or Voltage Contrast Scanning Electron Microscopy (VCSEM), techniques which are popular with the reverse engineer.
In the prior art, coatings have also been used to try to protect ICs from reverse engineering. And also it is known in the prior art to scramble the address lines, which will slow down, but not really thwart, the reverse engineer. Moreover, these techniques are primarily aimed at protecting data stored in ICs where the bit lines and address lines are buried on the IC so that the data can not be easily read out by making external connections to the IC.
Since the time and energy required to develop new data is considerable, reverse engineering has its followers. Indeed, the reverse engineer""s object is to make a slavish copy of the original data. The reverse engineer does not seem to be deterred by the fact that in many countries ICs are legally protected against copying by some form of mask work protection and that data is often protected against copying by a copyright law. As such, in order to protect the considerable investment made in data and in IC designs using such data, other or additional steps are needed to deter such slavish copying.
The prior art includes U.S. Pat. No. 5,866,933 to Baukus, Chow and Clark which teaches how transistors in a CMOS circuit are connected by implanted (therefore hidden and buried) lines between the transistors, via modifying the p+and n+source/drain masks. These implanted interconnections are further used to make a 3-input AND and OR circuit look substantially the same.
The prior art also includes U.S. Pat. Nos. 5,783,846 and 5,930,663 to Baukus, Chow and Clark, which teach a further modification in the source/drain implant masks so that the implanted connecting lines between transistors have a gap inserted with approximately the length of the minimum feature size of the CMOS technology being used. If this gap isxe2x80x9cfilledxe2x80x9d with one kind of implant (depending on the implanted connecting line being p or n) the line conducts; but, if it is filled with the other kind of implant the line does not conduct. These gaps are calledxe2x80x9cchannel blocks.xe2x80x9d Their use requires the reverse engineer to determine connectivity on the basis of resolving the n or p implant at the minimum feature size of the channel block. Further, the geometrical ambiguity technique in U.S. Pat. No. 5,866,933 is extended by modifying the transistor sizes, and metal connection routings to eliminate keys by which the reverse engineer can find inputs, outputs, gate lines etc. that help determine circuit functionality.
In one aspect, the present invention provides a circuit and a method for blocking unauthorized access to at least one memory cell in a semiconductor memory. The circuit and method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
In another aspect, the present invention provides a circuit for blocking access to a data line associated with at least one memory cell, the circuit preferably comprising: a first transistor coupling the data line to a constant voltage source when the first transistor is conductive; a second transistor coupled in series with a link and/or a switch, the link and/or the switch having an open circuit state and a closed circuit state; and an inverter having an input coupled to a junction between the second transistor and the link and/or the switch, the inverter having an output coupled to a gate of the first transistor and also to a gate of the second transistor.